A photo lithography process is one of the important tools employable for producing a semiconductor device. The photo lithography process consists of a step to spin coat a photo resist to produce a photo resist layer on a semiconductor substrate or layer, a step to expose a selected area of the photo resist layer, a step to develop the exposed photo resist layer to produce a photo resist pattern, a step to etch a selected portion of the semiconductor substrate or layer which selected portion is unconcealed by the photo resist pattern, and a step to remove the photo resist pattern which was employed as the etching mask in the previous etching step. The former half of the photo lithography process can be employed to produce a mask employable for an ion implantation process. In other words, a resist pattern produced by selective exposure of a resist layer can be employed as a mask for an ion implantation process employable for introducing impurities in the surface region of a semiconductor substrate or layer. An ashing process conducted employing oxygen radicals or oxygen plasma containing oxygen ions, is usually employed to remove the resist pattern, after an ion implantation process is finished employing the resist pattern as a mask. Since the ashing rate of such an ashing process is accelerated by temperature, it is preferable to conduct such an ashing process under a high temperature.
An ion implantation process conducted employing a resist pattern as a mask is accompanied by a phenomenon to reform the chemical composition of the substance of the top surface of the resist pattern. In other words, the top surface of the resist pattern is converted to a hardened layer, during an ion implantation process.
When a semiconductor substrate or layer selectively covered by a resist pattern of which the top surface has been converted to a hardened layer, is heated up to a high temperature e.g. 150.degree. C. or higher in an ashing apparatus for the purpose to remove the resist pattern, the hardened layer is broken by a high pressure caused by expansion of an evaporated substance located under the hardened layer. This explosive destruction of the hardened layer covering a resist pattern is called popping phenomenon. The popping phenomenon causes dispersion of resist particles, further causing contamination of the surface of the semiconductor substrate or layer and contamination of the internal surface of the ashing apparatus.
An ashing process conducted employing plasma under a low temperature for the purpose to remove an exposed resist pattern covered by a hardened layer, while avoiding popping phenomenon, is readily accompanied by a less ashing rate, resulting in a less magnitude of throughput.
Accordingly, a long standing requirement in this technical field is development of an ashing process for removing a resist pattern which was employed as a mask for an ion implantation process and is covered by a hardened layer and an apparatus employable therefor, both of which are free from popping phenomenon.